MediaTek Dimensity 9500 SoC Tipped to Supply Improved Ray Tracing and AI Efficiency; Specs Leak

Dimensity 9500 SoC is rumoured to be in improvement as the newest flagship-tier smartphone processor from MediaTek. Forward of its anticipated debut someday later this yr, a tipster means that it could possibly be fabricated utilizing TSMC’s N3P course of (3nm). Powered by Arm’s newest Cortex-X9 sequence cores, the chipset is alleged to carry enhancements associated to ray tracing and synthetic intelligence (AI) — the latter supported by a neural processing unit (NPU) able to delivering 100 tera operations per second (TOPS) efficiency.

Tipster Digital Chat Station (translated from Chinese language) leaked specs of the purported MediaTek Dimensity 9500 chipset in a put up on the Chinese language microblogging platform Weibo. Fabricated utilizing the N3P course of, the SoC is tipped to come back with an octa-core structure, although its make-up could possibly be totally different in comparison with what earlier rumours advised.

As a substitute of getting a 2 + 6 configuration, the Dimensity 9500 chipset might have one Cortex-X930 prime cores dubbed “Travis”, three cores dubbed “Alto”, and 4 Cortex-A730 “Gelas” cores.

The SoC is alleged to be complemented by an Immortalis-Drage GPU which may supply enhancements when it comes to ray tracing and AI, whereas additionally lowering the facility consumption, courtesy of a brand new GPU microarchitecture. In the meantime, an NPU 9.0 is tipped to ship 100 TOPS of AI efficiency. As per the tipster, the Dimensity 9500 chipset may have 16MB of L3 cache and 10MB of SLC cache. Touted to be a flagship providing, it might assist gadgets geared up with as much as LPDDR5X RAM and as much as UFS 4.1 storage.

Previous stories counsel that the N3P course of utilized by TSMC for the purported chipset’s fabrication may lead to a 5 p.c efficiency achieve and a 5-10 p.c effectivity enchancment as in comparison with the present Dimensity 9400 SoC which is constructed utilizing the N3E course of. It might additionally profit from improved multi-thread efficiency with using Arm’s Scalable Matrix Extension (SME) which might speed up AI and ML-based purposes and supply enhanced assist for matrix operations.

Though no official particulars are identified concerning the launch timeline of the Dimensity 9500 SoC, its predecessor was introduced in October 2024, and the purported chip may additionally launch across the similar time this yr.